In a three-phase brushless DC motor drive circuit, switching elements in a three-phase inverter circuit are turned on and off by PWM control in order to drive a motor. An example of such a three-phase brushless DC motor drive circuit is disclosed in Patent Document 1. In this example, a pair of MOSFETs is provided for controlling each of the three phases, wherein the MOSFETs are turned on and off in order to control the driving of a motor. Specifically, each pair of the MOSFETs for the respective phase is connected in series as switching elements between a motor-driving power supply and ground. In the following, the MOSFETs on the motor-driving power supply side are referred to as “upper-stage elements”, while the MOSFETs on the ground end side are referred to as “lower-stage elements”. If an upper-stage element and a lower-stage element for a phase are simultaneously turned on, a large current flows between the power supply and ground, thereby damaging the elements. Thus, when an on- or off-state of an upper-stage element and a lower-stage element is switched, a period referred to as a “dead time” is provided in which both the upper-stage element and the lower-stage element are turned off so as to prevent the damage to these elements. However, if the dead time is too long, disadvantages such as decreased efficiency and torque, and increased acceleration time may result. If the dead time is too short, the MOSFETs may be damaged. Thus, it is necessary to set an appropriate dead time for the particular system.
FIG. 1 is a graph indicating the relationship between an input duty ratio of a PWM signal inputted to a system and an output duty ratio of an output signal to a motor, where the positive and negative values on the vertical axis and the horizontal axis show the duty ratio during positive and negative rotations, respectively, of the motor. Referring to FIG. 1, when there is no dead time, the characteristics are linear, as indicated by the broken line. When there is a dead time, linear characteristics are not obtained in a region A1 (when the duty ratio is small) or regions A2 and A3 (when the duty ratio is high) due to the influence of the dead time. Thus, the longer the dead time, the longer a control-disabled region (dead-zone) becomes when the duty ratio is low, and the lower the maximum output duty ratio becomes when the duty ratio is high. Therefore, when the dead time is too long, stability is reduced when the motor is driven at low speed or upon reversal of rotation direction. As a result, the acceleration time at the starting of the motor increases, and controllability is reduced. Thus, the dead time should be minimized.
Controllability also suffers if the length of the dead time during the transition from a first state in which the upper-stage element is on and the lower-stage element is off to a second state in which the upper-stage element is off and the lower-stage element is on is different from the length of the dead time during the transition in the opposite direction (i.e., from the second to the first state). Thus, it is also desirable to set these dead times to have the same length from the viewpoint of controllability.
When an on- or off-status of the MOSFETs is fixed, there would be no problem if the on/off-controlled phases are changed in synchronization with the dead time.
However, if the rotation direction of the motor is changed, or a brake control is performed (by turning on all of the lower-stage elements of the three-phase inverter circuit, for example) in the absence of a dead time, the state of the upper-stage element and the state of the lower-stage element are simultaneously changed, thereby possibly damaging the elements. Therefore, a dead time needs to be ensured.
FIG. 2 is a circuit diagram of a dead-time generating circuit 200 according to Patent Document 2. The dead-time generating circuit 200 is fed with a control signal Sa from an external circuit (not shown) and outputs a control signal Pout for the upper-stage element and a control signal Nout for the lower-stage element of a three-phase inverter circuit. The dead-time generating circuit 200 includes a current mirror circuit 201, a delay time setting circuit 202, and an external resistor R10 connected to a terminal Tm10. The external resistor R10 sets a current that is outputted by the current mirror circuit 201. The delay time setting circuit 202 includes capacitors C11 and C12; discharge transistors T21 and T22 connected in parallel to the capacitors C11 and C12, respectively; buffers L12 and L13 configured to compare voltages V11 and V12 of the capacitors C11 and C12 with a threshold voltage so as to output on- or off-control signals Pout and Nout; and an inverter L11 for inverting the control signal Sa.
When the control signal Sa rises, the discharge transistor T21 turns on, so that the capacitor C11 is discharged. At the same time, the discharge transistor T22 turns off, so that the capacitor C12 is charged by the current outputted by the current mirror circuit 201. When the capacitor C11 is discharged and the voltage of the capacitor C11 drops below the threshold voltage of the buffer L12, the control signal Pout becomes an off-signal. On the other hand, when the capacitor C12 is charged and the voltage of the capacitor C12 exceeds the threshold voltage of the buffer L13, the control signal Nout becomes an on-signal. When the control signal Sa falls, the dead-time generating circuit 200 operates similarly as described above, with the operations of the discharge transistor T21 and the capacitor C11 and the operations of the discharge transistor T22 and the capacitor C12 switched. Thus, in the dead-time generating circuit 200, two dead times are generated, starting from the rise and fall timings of the control signal Sa, based on the time in which the capacitors C11 and C12 are charged. Because the magnitude of the current outputted by the current mirror circuit 201 can be set by the external resistor R10, the length of the dead time can be varied by changing the external resistor R10.
In the dead-time generating circuit 200 according to Patent Document 2, even if the capacitors C11 and C12 and the buffers L12 and L13 are designed such that the dead times starting from the rise and fall timings of the control signal Sa can have the same length, the threshold voltages for switching the on- and off-status of the control outputs Pout and Nout may vary due to various reasons. For example, variations may be introduced in the elements during a semiconductor manufacturing process. Also, the threshold voltages may be varied due to the fact that the buffer L12 is an inverter and has a different structure from the structure of the buffer L13. As a result, the two dead times may have different lengths.
FIG. 3 is a timing chart illustrating an operation of the dead-time generating circuit 200 illustrated in FIG. 2 when the threshold voltages are different. When the buffer L12 and the buffer L13 both have the same threshold voltage Vth1, the length of the dead time starting at the rise and fall timings of the control signal Sa is the same time t1. However, when the buffer L12 has a threshold voltage Vth2 lower than the threshold voltage Vth1, the dead time starting at the fall timing of the control signal Sa has a time t2 that is shorter than the length of the dead time t1 starting at the rise timing of the control signal Sa.
In Patent Document 2, it is also described that the length of the dead time does not vary even if the control signal Sa has a narrow pulse width shorter than the discharge times of the capacitors C11 and C12. In Patent Document 2, the time required for discharging the capacitors C11 and C12 is considered zero. However, discharging the capacitors C11 and C12 actually requires at least several to several dozen ns (nanoseconds), depending on the transistor characteristics of the capacitors C11 and C12, the elements for driving the control signal Sa, and a buffer L11. FIG. 4 is a timing chart illustrating an operation in a case where the dead-time generating circuit 200 illustrated in FIG. 2 is fed with a control signal Sa whose H-level period is shorter than the discharge time of the capacitor C11. In this case, because the period in which the control signal Sa has a H-level is shorter than the time required for discharging the capacitor C11, the control signal Sa assumes a L-level when the capacitor C11 is still being discharged, so that the voltage of the capacitor C11 does not drop below the threshold voltage Vth1. Thus, the control signal Pout is fixed to an on-status while the control signal Nout is fixed to an off-status. FIG. 5 is a timing chart illustrating an operation of the dead-time generating circuit 200 of FIG. 2 when a L-level period of a control signal Sa is shorter than the discharge time of the capacitor C12. In this case, too, because the period in which the control signal Sa has a L-level is shorter than the time required for discharging the capacitor C12, the voltage of the capacitor C12 does not drop below the threshold voltage Vth1. As a result, the control signal Pout is fixed to an off-status, while the control signal Nout is fixed to an on-status.
As described above, in either case, neither the capacitor C11 nor the capacitor C12 are discharged below the threshold voltage Vth1, so that the control signals Pout and Nout do not change. When a three-phase brushless DC motor is controlled, a control signal status needs to be changed upon change in rotation direction or during a brake control while ensuring a dead time. Therefore, when the dead-time generating circuit 200 according to Patent Document 2 is applied for controlling a brushless DC motor, if the control signal Sa has a short pulse such that the dead time for the capacitor C11 or C12 cannot be ensured, it may become impossible to perform rotation direction control or brake control, for example.
Patent Document 1: JP2003-289687A
Patent Document 2: JP2003-051740A